1. Field of the Invention
The present invention relates to a memory device comprising an array of memory cells, and to a method of performing a read operation within such a memory device.
2. Description of the Prior Art
As process geometries shrink in modern data processing systems, the variability in the operating characteristics of the individual circuit elements increases. Considering as an example a memory device consisting of an array of memory cells, it will be understood that each memory cell will typically consist of a number of electronic components such as transistors, and the variability in those individual components significantly increases as process geometries shrink. Furthermore, there is an increasing desire to operate data processing systems at lower and lower supply voltages, but as the supply voltage decreases, reliability issues due to the variations in the individual components become more prominent.
One reliability concern arises from the fact that leakage current can increase within the individual memory cells as the process geometries shrink, and this can potentially give rise to incorrect operation. Considering as an example a single-ended memory cell, such a memory cell uses a single read bit line coupled to an internal node of the memory cell to allow the data value stored in that memory cell to be read during a read operation. The single read bit line is precharged to a first voltage level (typically the supply voltage Vdd) and then if a memory cell coupled to that read bit line is addressed during a read operation (by an asserted read word line signal on the read word line to which that memory cell is coupled), the voltage on the bit line will either stay at the first voltage level, or will discharge towards the second voltage level, depending on the value stored within the memory cell. During the period that the read word line signal is asserted, a sense amplifier connected to the read bit line monitors the voltage on the read bit line, and if the voltage transitions to a trip voltage level between the first and second voltage levels whilst the read word line signal is asserted, the sense amplifier will determine that the memory cell stores a first value, whilst if it does not transition to the trip voltage level the sense amplifier will determine that the memory cell stores a second value.
However, any particular read bit line will typically have multiple memory cells within a particular column of the array coupled to it, with only one of those memory cells being addressed during a particular read operation. During the read operation, there will be some leakage current due to those memory cells coupled to the read bit line, with the amount of leakage current depending on a number of factors, for example the data values stored within those memory cells. As the process geometries shrink, the leakage current tends to increase, and in some instances the leakage current can be significant enough that even though the addressed memory cell stores the second value, and accordingly the voltage on the read bit line should be retained at the first voltage level, the voltage on the read bit line starts to transition towards the second voltage level due to the leakage current, and may in fact reach the trip voltage level whilst the read word line is still asserted. In that instance, the sense amplifier will incorrectly determine that the addressed memory cell stores the first value (even though it in fact stores the second value).
One known approach to guard against this possibility is to provide bit line keeper circuitry that is connected to the read bit line, and which serves to weakly pull the bit line towards the first voltage level during the read operation. If the addressed memory cell does store the first value, it will overcome the weak pull of the bit line keeper circuitry, and accordingly the voltage will transition to the trip voltage level during the read operation. However, the leakage current effects will not be strong enough to overcome the weak pull of the bit line keeper, accordingly avoiding a potential incorrect sensing of the data value by the sense amplifier circuitry. However, whilst the addressed memory cell can overcome the weak pull of the bit line keeper circuitry if it does store the first value, the weak pull of the bit line keeper circuitry nevertheless impacts the speed with which the voltage on the read bit line transitions from the first voltage level towards the second voltage level, and accordingly impacts the performance of the read operation.
To avoid this impact on read performance, it would be necessary to make the memory cells significantly larger in order to enable them to more quickly overcome the effect of the bit line keeper circuitry. However, if the memory cells are made larger, this increases the area and power consumption of the memory device, which is undesirable.
Accordingly, it would be desirable to provide an improved technique for performing a read operation within a memory device.